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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. november 1994 copyright ? intel corporation, 1996 order number: 231428-006 upi-452 chmos programmable i/o processor 83c452 - 8k c 8 mask programmable internal rom 80c452 - external rom/eprom y 83c452/80c452:3.5 to 14 mhz clock rate y software compatible with the mcs-51 family y 128-byte bi-directional fifo slave interface y two dma channels y 256 c 8-bit internal ram y 34 additional special function registers y 40 programmable i/o lines y two 16-bit timer/counters y boolean processor y bit addressable ram y 8 interrupt sources y programmable full duplex serial channel y 64k program memory space y 64k data memory space y 68-pin pga and plcc (see packaging spec., order: y 231369) the intel upi-452 (universal peripheral interface) is a 68 pin chmos slave i/o processor with a sophisticated bi-directional fifo buffer interface on the slave bus and a two channel dma processor on-chip. the upi-452 is the newest member of intel's upi family of products. it is a general-purpose slave i/o processor that allows the designer to grow a customized interface solution. the upi-452 contains a complete 80c51 with twice the on-chip data and program memory. the sophisticated slave fifo module acts as a buffer between the upi-452 internal cpu and the external host cpu. to both the external host and the internal cpu, the fifo module looks like a bi-directional bottomless buffer that can both read and write data. the fifo manages the transfer of data independent of the upi-452 core cpu and generates an interrupt or dma request to either cpu, host or internal, as a fifo service request. the fifo consists of two channels:the input fifo and the output fifo. the division of the fifo module array, 128 bytes, between input channel and output channel is programmable by the user. each fifo byte has an additional logical ninth bit to distinguish between a data byte and a data stream command byte. additionally, immediate commands allow direct, interrupt driven, bi-directional communication between the upi-452 internal cpu and external host cpu, bypassing the fifo. the on-chip dma processor allows high speed data transfers from one writeable memory space to another. as many as 64k bytes can be transferred in a single dma operation. three distinct memory spaces may be used in dma operations; internal data memory, external data memory, and the special function registers (including the fifo in, fifo out, and serial channel special functions registers).
upi-452 231428 1 figure 1. architectural block diagram 2
upi-452 231428 2 figure 1. architectural block diagram (continued) 3
upi-452 table of contents contents page introduction 1 table of contents 4 list of tables and figures 5 pin description 7 architectural overview 10 introduction 10 fifo buffer interface 10 fifo programmable features 11 immediate commands 12 dma 12 fifo/slave interface functional description 12 overview 12 input fifo channel 13 output fifo channel 14 immediate commands 16 host & slave interface special function registers 18 slave interface special function registers 18 external host interface special function registers 20 fifo moduleeexternal host interface 22 overview 22 slave interface address decoding 22 interrupts to the host 22 dma requests to the host 24 fifo moduleeinternal cpu interface 24 overview 24 internal cpu access to fifo via software instructions 24 general purpose dma channels 25 overview 25 architecture 25 dma special function registers 26 dma transfer modes 27 external memory dma 29 latency 29 dma interrupt vectors 29 interrupts when dma is active 30 dma arbitration 30 interrupts 32 overview 32 fifo module interrupts to internal cpu 32 interrupt enabling and priority 33 fifoeexternal host interface fifo dma freeze mode 35 overview 35 initialization 35 invoking fifo dma freeze mode during normal operation 36 fifo module special function register operation during fifo dma freeze mode 37 internal cpu read & write of the fifo during fifo dma freeze mode 41 memory organization 41 accessing external memory 41 miscellaneous special function register descriptions 43 4
upi-452 list of tables and figures figures: 1. architectural block diagram 2 2. upi 452 68-pin plcc pinout diagram 6 3. upi-452 conceptual block diagram 10 4. upi-452 functional block diagram 11 5. input fifo channel functional block diagram 13 6. output fifo channel functional block diagram 15 7a. handshake mechanisms for handling immediate command in flowchart 17 7b. handshake mechanisms for handling immediate command out flowchart 17 8. dma transfer from: external to external memory 31 9. dma transfer from: external to internal memory 31 10. dma transfer from: internal to external memory 31 11. dma transfer waveform: internal to internal memory 32 12. disabling fifo to host slave interface timing diagram 36 tables: 1. input fifo channel registers 13 2. output fifo channel registers 15 3. upi-452 address decoding 23 4. dma accessible special function registers 26 5. dma mode control - pcon sfr 29 6. interrupt priority 32 7. interrupt vector addresses 32 8. slave bus interface status during fifo dma freeze mode 35 9. fifo sfr's characteristics during fifo dma freeze mode 38 10. threshold sfrs range of values and number of bytes to be transferred 39 11a. internal memory addressing 41 11b. 80c51 special function registers 42 11c. upi-452 additional special function registers 42 12. program status word (psw) 44 13. pcon special function register 44 5
upi-452 p.c. board vieweas viewed from the component side of the p.c. board (underside of socket) 231428 32 figure 2. upi 452 68-pin plcc pinout diagram 6
upi-452 upi microcontroller family the upi-452 joins the current members of the upi microcontroller family. upi's are derivatives of the mcs tm family of microcontrollers. because of their on-chip system bus interface, upi's are designed to be system bus ``slaves'', while their microcontroller counterparts are intended as system bus ``masters''. these upi microcontrollers are fully supported by intel's development tools (ice, asm and plm). packaging the 80c452/83c452 is available in a 68-pin plcc package. upi family mcs family ram rom (slave (master speed (bytes) (bytes) configuration) configuration) 80c452 80c51 12 mhz 256 e 83c452 80c51 12 mhz 256 8k 80c452-1 80c51 14 mhz 256 e 83c452-1 80c51 14 mhz 256 8k upi-452 pin descriptions symbol pin y type name and function v ss 9/43 i circuit ground. v cc 60 i a 5v power supply during normal and idle mode operation. it is also the standby power pin for power down mode. xtal1 38 i input to the oscillator's high gain amplifier. a crystal or external source can be used. xtal2 39 o output from the high gain amplifier. port 0 i/o port 0 is an 8-bit open drain bi-directional i/o port. port 0 can sink (ad0 ad7) eight ls ttl inputs. it is also the multiplexed low-order address and p0.0 8 data local expansion bus during accesses to external memory. .1 10 .2 11 .3 12 .4 13 .5 14 .6 15 p0.7 16 7
upi-452 upi-452 pin descriptions (continued) symbol pin y type name and function port 1 i/o port 1 is an 8-bit quasi-bi-directional i/o port. port 1 can sink four (a0 a7) ls ttl inputs. the alternate functions can only be activated if the (hld , hlda ) corresponding bit latch in the port sfr contains a 1. otherwise, the p1.0 7 port pin is stuck at 0. pins p1.5 and p1.6 are multiplexed with hld and hlda respectively whose functions are defined as below: .1 6 port pin alternate function .2 5 p1.5 hld elocal bus hold .3 4 input/output signal .4 3 p1.6 hlda elocal bus hold .5 2 acknowledge input .6 1 p1.7 68 port 2 i/o port 2 is an 8-bit quasi-bi-directional i/o port. it also emits the high- (a8 a15) order 8 bits of address when accessing local expansion bus p2.0 29 external memory. port 2 can sink four ls ttl inputs. .1 28 .2 27 .3 25 .4 24 .5 23 .6 22 .7 21 port 3 i/o port 3 is an 8-bit quasi-bi-directional i/o port. it is also multiplexed p3.0 67 with the interrupt, timer, local serial channel, rd/ and wr/ .1 66 functions that are used by various options. the alternate functions .2 65 can only be activated if the corresponding bit latch in the port sfr .3 64 contains a 1. otherwise, the port pin is stuck at 0. port 3 can sink .4 63 four ls ttl inputs. the alternate functions assigned to the pins of .5 62 port 3 are as follows: .6 61 port pin alternate function p3.7 59 p3.0 rxd e serial input port p3.1 txd e serial output port p3.2 int0 e interrupt 0 input p3.3 int1 e interrupt 1 input p3.4 t0 e input to counter 0 p3.5 t1 e input to counter 1 p3.6 wr/ e the write control signal latches the data from port 0 outputs into the external data memory on the local bus. p3.7 rd/ e the read control signal latches the data from port 0 outputs on the local bus. 8
upi-452 upi-452 pin descriptions (continued) symbol pin y type name and function port 4 i/o port 4 is an 8-bit quasi-bi-directional i/o port. port 4 can sink/ p4.0 30 source four ttl inputs. .1 .2 32 .3 33 .4 34 .5 35 .6 36 .7 37 rst 20 i a high level on this pin for two machine cycles while the oscillator is running resets the device. an internal pulldown resistor permits power-on reset using only a capacitor connected to v cc . this pin does not receive the power down voltage as is the case for hmos mcs-51 family members. this function has been transferred to the v cc pin. ale 18 o provides address latch enable output used for latching the address into external memory during normal operation. ale can sink/source eight ls ttl inputs. psen 19 o the program store enable output is a control signal that enables the external program memory to the bus during normal fetch operation. psen can sink/source eight ls ttl inputs. ea 17 i when held at ttl high level, the upi-452 executes instructions from the internal rom when the pc is less than 8192 (8k, 2000h). when held at a ttl low level, the upi-452 fetches all instructions from external program memory. db0 58 i/o host bus interface is an 8-bit bi-directional bus. it is used to transfer db1 57 data and commands between the upi-452 and the host processor. db2 56 this bus can sink/source eight ls ttl inputs. db3 55 db4 54 db5 53 db6 52 db7 51 cs 44 i this pin is the chip select of the upi-452. a0 40 i these three address lines are used to interface with the host a1 41 system. they define the upi-452 operations. the interface is a2 42 compatible with the intel microprocessors and the multibus. read 46 i this pin is the read strobe from the host cpu. activating this pin causes the upi-452 to place the contents of the output fifo (either a command or data) or the host status/control special function register on the slave data bus. write 47 i this pin is the write strobe from the host. activating this pin will cause the value on the slave data bus to be written into the register specified by a0 a2. drqin/ 49 o this pin requests an input transfer from the host system whenever intrqin the input channel requires data. drqout/ 48 o this output pin requests an output transfer whenever the output intrqout channel requires service. if the external host to upi-452 dma is enabled, and a data stream command is at the output fifo, drqout is deactivated and intrq is activated (see `general purpose dma channels' section). 9
upi-452 upi-452 pin descriptions (continued) symbol pin y type name and function intrq 50 o this output pin is used to interrupt the host processor when an immediate command out or an error condition is encountered. it is also used to interrupt the host processor when the fifo requests service if the dma is disabled and intrqin and intrqout are not used. dack 45 i this pin is the dma acknowledge for the host bus interface input and output channels. when activated, a write command will cause the data on the slave data bus to be written as data to the input channel (to the input fifo). a read command will cause the output channel to output data (from the output fifo) on to the slave data bus. this pin should be driven high ( a 5v) in systems which do not have a dma controller (see address decoding). v cc 26 i a 5v power supply during operation. architectural overview introduction the upi-452 slave microcontroller incorporates an 80c51 with double the program and data memory, a slave interface which allows it to be connected di- rectly to the host system bus as a peripheral, a fifo buffer module, a two channel dma processor, and a fifth i/o port (figure 3). the upi-452 retains all of the 80c51 architecture, and is fully compatible with the mcs-51 instruction set. the special function register (sfr) interface con- cept introduced in the mcs-51 family of microcon- trollers has been expanded in the upi-452. to the 20 special function registers of the mcs-51, the upi-452 adds 34 more. these additional special function registers, like those of the mcs-51, pro- vide access to the upi-452 functional elements in- cluding the fifo, dma and added interrupt capabili- ties. several of the 80c51 core special function registers have also been expanded to support add- ed features of the upi-452. this data sheet describes the unique features of the upi-452. refer to the 80c51 data sheet for a de- scription of the upi-452's core cpu functional blocks including; e timers/counters e i/o ports e interrupt timing and control (other than fifo and dma interrupts) e serial channel e local expansion bus e program/data memory structure e power-saving modes of operation e chmos features e instruction set figure 3 contains a conceptual block diagram of the upi-452. figure 4 provides a functional block dia- gram. fifo buffer interface a unique feature of the upi-452 is the incorporation of a 128 byte fifo array at the host-slave interface. the fifo allows asynchronous bi-directional trans- fers between the host cpu and the internal cpu. 231428 7 figure 3. upi-452 conceptual block diagram 10
upi-452 231428 8 figure 4. upi-452 functional block diagram the division of the 128 bytes between input and output channels is user programmable allowing maximum flexibility. if the entire 128 byte fifo is allocated to the input channel, a high performance host can transfer up to 128 bytes at one time, then dedicate its resources to other functions while the internal cpu processes the data in the fifo. vari- ous handshake signals allow the external host to operate independently and without frequent monitor- ing of the upi-452 internal cpu. the fifo buffer insures that the slave processor receives data in the same order that it was sent by the host without the need to keep track of addresses. three slave bus interface handshake methods are supported by the upi-452: dma, interrupt and polled. the fifo is nine bits wide. the ninth bit acts as a command/data flag. commands written to the fifo by either the host or internal cpu are called data stream commands or dscs. dscs are written to the input fifo by the host via a unique external address. dscs are written to the output fifo by the internal cpu via the command out special func- tion register (sfr). when encountered by the host or internal cpu a data stream command can be used as an address vector to user defined service routines. dscs provide synchronization of data and commands between the host and internal cpu. fifo programmable features size of input/output channels the 128 bytes of fifo space can be allocated be- tween the input and output channels via the chan- nel boundary pointer (cbp) sfr. this register con- tains the number of address locations assigned to the input channel. the remaining address locations are automatically assigned to the output fifo. the cbp sfr can only be programmed by the internal cpu during fifo dma freeze mode (see fifo-ex- ternal host interface fifo dma freeze mode de- scription). the cbp is initialized to 40h (64 bytes) upon reset. the number in the channel boundary pointer sfr is actually the first address location of the output fifo. writing to the cbp sfr reassigns the input and output fifo address space. whenever the cbp is written, the input fifo pointers are reset to zero and the output fifo pointers are set to the value in the cbp sfr. all of the fifo space may be assigned to one chan- nel. in such a situation the other channel's data path consists of a single sfr (fifo in/command in or fifo out/command out sfr) location. cbp input fifo output fifo register size size 0 1 128 1 1 128 2 2 126 3 3 125 4 4 124 ## # 7b 123 5 7c 124 4 7d 125 3 7e 128 1 7f 128 1 11
upi-452 fifo read/write pointers these normally operate in auto-increment (and auto- rollover) mode, but can be reassigned by the internal cpu during fifo dma freeze mode (see fifo-ex- ternal host interface fifo dma freeze mode de- scription). threshold register the input fifo threshold sfr contains the number of empty bytes that must be available in the input fifo to generate a host interrupt. the output fifo threshold sfr contains the number of bytes, data and/or dsc(s), that must be in the fifo before an interrupt is generated. the threshold feature pre- vents the host from being interrupted each time the fifo needs to load or unload one byte of data. the thresholds, therefore, allow the fifo's operation to be adjusted to the speed of the host, optimizing the overall interface performance. note: dsc's should be allowed to be written into the out- put fifo by the upi-452 code only when the serv- ice request is law. the service request can be mon- itored by b7 of othr. this guideline will elimate the possibility of a dsc being written to the output fifo with the intention of setting the service re- quest while having the number of bytes in the out- put fifo below the threshold. this condition can occur if the fifo contains at least two bytes, the service request is being asserted, and the host reads from the output fifo until one byte remains. immediate commands the upi-452 provides, in addition to data and dscs, a third direct means of communication between the external host and internal cpu called immediate commands. as the name implies, an immediate command is available to the receiving cpu immedi- ately, via an interrupt, without being entered into the fifo as are data stream commands. like data stream commands, immediate commands are writ- ten either via a unique external address by the host cpu, or via dedicated sfr by the internal cpu. the dsc and/or immediate command interface may be defined as either interrupt or polled under user program control via the interrupt enable (ie), slave control register (slcon), and interrupt en- able priority (iep) special function registers, for the internal cpu and via the host control sfr for the external host cpu. dma the upi-452 contains a two channel internal dma controller which allows transfer of data between any of the three writeable memory spaces: internal data memory, external load expansion bus data memo- ry and the special function register array. the spe- cial function register array appears as a set of unique dedicated memory addresses which may be used as either the source or destination address of a dma transfer. each dma channel is independently programmable via dedicated special function reg- isters for mode, source and destination addresses, and byte count to be transferred. each dma channel has four programmable modes: e alternate cycle mode e burst mode e fifo or serial channel demand mode e external demand mode a complete description of each mode and dma op- eration may be found in the section titled ``general purpose dma channels''. fifo/slave interface functional description overview the fifo is a 128 byte ram array with recirculating pointers to manage the read and write accesses. the fifo consists of an input and an output chan- nel. access cycles to the fifo by the internal cpu and external host are interleaved and appear to be occurring concurrently to both the internal cpu and external host. interleaving access cycles ensures efficient use of this shared resource. the internal cpu accesses the fifo in the same way it would access any of the special function registers e.g., direct and register indirect addressing as well as ar- ithmetric and logical instructions. 12
upi-452 input fifo channel the input fifo channel provides for data transfer from the external host to the internal cpu (figure 5). the registers associated with the input channel during normal operation are listed in table 1 * . table 1. input fifo channel registers * register name description 1) input buffer latch host cpu write only 2) fifo in sfr internal cpu read only 3) command in sfr internal cpu read only 4) input fifo read pointer sfr internal cpu read only 5) input fifo write pointer sfr internal cpu read only 6) input fifo threshold sfr internal cpu read only * see ``fifo-external host interface fifo dma freeze mode'' section for fifo dma freeze mode sfr characteristics description. 231428 9 figure 5. input fifo channel functional block diagram 13
upi-452 the host cpu writes data and data stream com- mands into the input buffer latch on the rising edge of the external wr signal. external addressing de- termines whether the byte is a data byte or data stream command and the fifo logic sets the ninth bit of the fifo accordingly as the byte is moved from the input buffer latch into the fifo. a ``1'' in the ninth bit indicates that the incoming byte is a data stream command. the internal cpu reads data bytes via the fifo in sfr, and data stream commands via the command in sfr. a data stream command will generate an interrupt to the internal cpu prior to being read and after completion of the previous operation. the dsc can then be read via the command in sfr. data can only be read via the fifo in sfr and data stream commands via the command in sfr. attempting to read data stream commands as data by address- ing the fifo in sfr will result in ``0ffh'' being read, and the input fifo read pointer will remain intact. (this prevents accidental misreading of data stream commands.) attempting to read data as data stream commands will have the same conse- quence. the input fifo channel addressing is controlled by the input fifo read and write pointer sfrs. these sfrs are read only registers during normal opera- tion. however, during fifo dma freeze mode (see fifo-external host interface fifo dma freeze mode description), the internal cpu has write ac- cess to them. any write to these registers in normal mode will have no effect. the input write pointer sfr contains the address location to which data/ commands are written from the input buffer latch. the write pointer is automatically incremented after each write and is reset to zero if equal to the cbp, as the input fifo operates as a circular buffer. if a write is performed on an empty fifo, the first byte is also written into the fifo in or command in sfr. if the host continues writing while the input fifo is full, an external interrupt, if enabled, is sent to the host to signal the overrun condition. the writes are ignored by the fifo control logic. similar- ly, an internal cpu read of an empty fifo will cause an underrun error interrupt to be generated to the internal cpu and a value of ``0ffh'' will be read by the internal cpu. the read pointer sfr holds the address of the next byte to be read from the input fifo. an input fifo read operation post-increments the input read pointer sfr and loads a new data byte into the fifo in sfr or a data stream command into the command in sfr at the end of the read cycle. an input fifo request for service (via dma, inter- rupt or a flag) is generated to the host whenever more data can be written into the input fifo. for efficient utilization of the host, a ``threshold'' value can be programmed into the input fifo threshold sfr. the range of values of the input fifo thresh- old sfr can be from 0 to (cbp-3). the request for service interrupt is generated only after the input fifo has room to accommodate a threshold number of bytes or more. the threshold is equal to the total number of bytes assigned to the input fifo (cbp) minus the number of bytes programmed in the input fifo threshold sfr. with this feature the host is assured that it can write at least a threshold number of bytes to the input fifo channel without worrying about an overrun condition. once the request for service is generated it remains active until the input fifo becomes full. output fifo channel the output fifo channel provides data transfer from the upi-452 internal cpu to the external host (figure 6). the registers associated with the output channel during normal operation are listed in table 2 * . 14
upi-452 231428 10 figure 6. output fifo channel functional block diagram table 2. output fifo channel registers register name description 1) output buffer latch host cpu read only 2) fifo out sfr internal cpu read and write 3) command out sfr internal cpu read and write 4) output fifo read pointer sfr internal cpu read only 5) output fifo write pointer sfr internal cpu read only 6) output fifo threshold sfr internal cpu read only * see ``fifo-external host interface fifo dma freeze mode'' section for fifo dma freeze mode register characteristics description. 15
upi-452 the upi-452 internal cpu transfers data to the out- put fifo via the fifo out sfr and commands via the command out sfr. if the byte is written to the command out sfr, the ninth bit is automati- cally set ( e 1) to indicate a data stream command. if the byte is written to the fifo out sfr the ninth bit is cleared ( e 0). thus the fifo out and com- mand out sfrs are the same but the address de- termines whether the byte entered in the fifo is a dsc or data byte. the output fifo preloads a byte into the output buffer latch. when the host issues a rd/ signal, the data is immediately read from the output buffer latch. the next data byte is then loaded into the output buffer latch, a flag is set and an interrupt, if enabled, is generated if the byte is a dsc (ninth bit is set). the operation is carefully timed such that an interrupt can be generated in time for it to be recog- nized by the host before its next read instruction. internal cpu write and external host read opera- tions are interleaved at the fifo so that they appear to be occurring concurrently. the output fifo read and write pointer operation is the same as for the input channel. writing to the fifo out or command out sfrs will increment the output write pointer sfr but reading from it will leave the write pointer unchanged. a rollover of the output fifo write pointer causes the pointer to be reset to the value in the channel boundary pointer (cbp) sfr. if the external host attempts to read a data stream command as a data byte it will result in invalid data (0ffh) being read. the dsc is not lost because the invalid read does not increment the pointer. similarly attempting to read a data byte as a data stream command has the same result. a request for service is generated to the external host under the following two conditions: 1.) whenever the internal cpu has written a thresh- old number of bytes or more into the output fifo (threshold e (othr) a 1). the threshold num- ber should be chosen such that the bus latency time for the external host does not result in a fifo overrun error condition on the internal cpu side. the threshold limit should be large enough to make a bus request by the upi-452 to the ex- ternal host cpu worthwhile. once a request for service is generated, the request remains active until the output fifo becomes empty. the range of values of the fifo output threshold (othr) sfr is from 2 to (80h-cbp)-1 . the threshold number can be programmed via the othr sfr. 2.) the second type of request for service is called ``flush mode'' and occurs when the internal cpu writes a data stream command into the output fifo. its purpose is to ensure that a data block entered into the output fifo, which is less than the programmed threshold, will generate a re- quest for service interrupt, if enabled, and be read, or ``flushed'' from the output fifo, by the external host cpu regardless of the status of the othr sfr. note: the host port read or write strobe (tpw) should be limited to a maximum of 4 tclcl. this guideline will eliminate a potential output fifo request lock- up from occurring if the host reads the last byte from the output fifo while the upi-452 is begin- ning to write another byte to the output fifo. immediate commands immediate commands provide direct communica- tion between the external host and upi-452. unlike data stream commands which are entered into the fifo, the immediate command is available to the receiving cpu directly, bypassing the fifo. the im- mediate command can serve as a program vector pointing into a jump table in the recipients software. immediate command interrupts are generated, if en- abled, and a bit in the appropriate status register is set when an immediate command is input or output. a similar bit is provided to acknowledge when an immediate command has been read and whether the register is available to receive another com- mand. the bits are reset when the immediate com- mands are read. two special function registers are dedicated to the immediate command interface. ex- ternal addressing determines whether the host is accessing the input fifo or the immediate com- mand in (imin) sfr. the internal cpu writes imme- diate commands to the immediate command out (imout) sfr. both processors have the ability to enable or disable immediate command interrupts. by disabling the in- terrupt, the recipient of the immediate command can poll the status sfr and read the immediate command at its convenience. immediate com- mands should only be written when the appropriate immediate command sfr is empty (as indicated in the appropriate status sfr:hstat/sstat). simi- larly, the immediate command sfr should only be read when there is data in the register. the flowcharts in figure 7a and 7b illustrate the proper handshake mechanisms between the exter- nal host and internal cpu when handling immediate commands. 16
upi-452 231428 11 figure 7a. handshake mechanisms for handling immediate command in flowchart 231428 12 figure 7b. handshake mechanisms for handling immediate command out flowchart 17
upi-452 host & slave interface special function registers slave interface special function registers the internal cpu interfaces with the fifo slave module via the following registers: 1) mode special function register (mode) 2) slave control special function register (slcon) 3) slave status special function register (sstat) each register resides in the sfr array and is accessible via all direct addressing modes except bit. only the slave control register (slcon) is bit addressable. 1) mode special function register (mode) the mode sfr provides the primary control of the external host-fifo interface. it is included in the sfr array so that the internal cpu can configure the external host-fifo interface should the user decide that the upi-452 slave initialize itself independent of the external host cpu. the mode sfr can be directly modified by the internal cpu through direct address instructions. it can also be indirectly modified by the external host cpu by setting up a mode sfr service routine in the upi-452 program memory and having the host issue a command, either immediate or dsc, to vector to that routine. symbolic physical address address mode e md6 md5 md4 e e e e 0f9h (msb) (lsb) status on reset: 1 * 0001 * 1 * 1 * 1 * md7 (reserved) ** md6 request for service to external cpu via; 1 e dma (drqin/drqout) request to external host when the input or output fifo channel re- quests service 0 e interrupt (intrqin/intrqout or intrq) to external host when the input or output fifo channel requests service or a dsc is encountered in the i/o buffer latch md5 configure drqin/intrqin and drqout/intrqout to be either; 1 e enable (actively driven) 0 e disable (tri-state) md4 configure intrq to be either; 1 e enable (actively driven) 0 e disable (tri-state) md3 (reserved) ** md2 (reserved) ** md1 (reserved) ** md0 (reserved) ** 2) slave control sfr (slcon) the slave control sfr is used to configure the fifo-internal cpu interface. all interrupts are to the internal cpu. 18
upi-452 symbolic physical address address slcon ifi ofi icii icoi frz e ifrs ofrs 0e8h (msb) (lsb) status on reset: 000001 * 00 ifi enable input fifo interrupt (due to underrun error condition, data stream command or request service) 1 e enable 0 e disable ofi enable output fifo interrupt (due to overrun error condition or request service) 1 e enable 0 e disable note: if the dma is configured to service a fifo demand, then the request for service interrupt is not generated. icii generate interrupt when a command is written to the immediate command in register 1 e enable 0 e disable icoi generate interrupt when immediate command out register is available 1 e enable 0 e disable frz enable fifo dma freeze mode 1 e normal operation 0 e fifo dma freeze mode sc2 (reserved) ** ifrs input fifo channel request for service 1 e request when input fifo not empty 0 e request when input fifo full ofrs output fifo channel request for service 1 e request when output fifo not full 0 e channel request when output fifo empty notes: * a `1' will be read from all sfr reserved locations except hcon sfr, hc0 and hc2. ** `reserved'ethese locations are reserved for future use by intel corporation. 3) slave status sfr (sstat) the bits in the slave status sfr reflect the status of the fifo-internal cpu interface. it can be read during an internal interrupt service routine to determine the nature of the interrupt or read during a polling sequence to determine a course of action. symbolic physical address address sstat sst7 sst6 sst5 sst4 sst3 sst2 sst1 sst0 0e9h w output fifo status xw input fifo status x status on reset: 1 0001111 (msb) (lsb) 19
upi-452 sst7 output fifo overrun error condition 1 e no error 0 e error (latched until slave status sfr is read) sst6 immediate command out register status 1 e full (i.e. host cpu has not read previous immediate command out sent by internal cpu) 0 e available sst5 fifo dma freeze mode status 1 e normal operation 0 e fifo dma freeze mode in progress sst4 output fifo request for service flag 1 e output fifo does not request service 0 e output fifo requests service sst3 input fifo underrun error condition flag 1 e no underrun error 0 e underrun error (latched until slave status sfr is read) sst2 immediate command in sfr status 1 e empty 0 e immediate command received from host cpu sst1 data stream command/data at input fifo flag 1 e data (not dsc) 0 e dsc (at command in sfr) sst0 input fifo request for service flag 1 e input fifo does not request service 0 e input fifo request for service external host interface special function registers the external host cpu has direct access to the following sfrs: 1) host control special function register 2) host status special function register it can also access other sfrs by commanding the internal cpu to change them accordingly via data stream commands or immediate commands. the protocol for implementing this is entirely determined by the user. 1) host control sfr (hcon) by writing to the host control sfr, the host can enable or disable fifo interrupts and dma requests and can reset the upi-452. symbolic physical address address hcon hc7 hc6 hc5 hc4 hc3 e hc1 e 0e7h (msb) (lsb) status on reset: 000000 * 00 * 20
upi-452 hc7 enable output fifo interrupt due to underrun error condition, data stream command or service request 1 e enable 0 e disable hc6 enable input fifo interrupt due to overrun error condition, or service request 1 e enable 0 e disable hc5 enable the generation of the interrupt due to immediate command out being present 1 e enable 0 e disable hc4 enable the interrupt due to the immediate command in register being available for a new immediate command byte 1 e enable 0 e disable hc3 reset upi-452 1 e software reset 0 e normal operation hc2 (reserved) ** hc1 select between intrq and intrqin/intrqout as request for service interrupt signal when dma is disabled 1 e intrq 0 e intrqin or intrqout hc0 (reserved) ** notes: * a `1' will be read from all sfr reserved locations except hcon sfr, hc0 and hc2. ** `reserved'ethese locations are reserved for future use by intel corporation. 2) host status sfr (hstat) the host status sfr provides information on the fifo-host interface and can be used to determine the source of an external interrupt during polling. like the slave status sfr, the host status sfr reflects the current status of the fifo-external host interface. symbolic physical address address hstat hst7 hst6 hst5 hst4 hst3 hst2 hst1 hst0 0e6h w output fifo status xw input fifo status x status on reset: 1 1 1 1 1 1/0 * 11 (msb) (lsb) 21
upi-452 hst7 output fifo underrun error condition 1 e no underrun error 0 e underrun error (latched until host status register is read) hst6 immediate command out sfr status 1 e empty 0 e immediate command present hst5 data stream command/data at output fifo status 1 e data (not dsc) 0 e dsc (present at output fifo com- mand out sfr) (note: only if hst4 e 0, if hst4 e 1 then un- determined) hst4 output fifo request for service status 1 e no request for service 0 e output fifo request for service due to: a. output fifo containing the threshold number of bytes or more b. internal cpu sending a block of data ter- minated by a dsc (dsc flush mode) hst3 input fifo overrun error condition 1 e no overrun error 0 e overrun error (latched until host status register is read) hst2 immediate command in sfr status 1 e full (i.e. internal cpu has not read pre- vious immediate command sent by host) 0 e empty * reset value; `1' e if read by the external host `0' e if read by internal cpu (reads shadow latch - see fifo dma freeze mode descrip- tion) hst1 fifo dma freeze mode status 1 e freeze mode in progress. (in freeze mode, the bits of the host status sfr are forced to a `1' initially to prevent the external host from attempting to access the fifo. the definition of the host status sfr bits during fifo dma freeze mode can be found in fifo dma freeze mode descrip- tion) 0 e normal operation hst0 input fifo request service status 1 e input fifo does not request service 0 e input fifo request service due to the input fifo containing enough space for the host to write the threshold number of bytes or more fifo module - external host interface overview the fifo-external host interface supports high speed asynchronous bi-directional 8-bit data trans- fers. the host interface is fully compatible with intel microprocessor local busses and with multibus. the fifo has two specialized dma request pins for input and output fifo channel dma requests. these are multiplexed to provide a dedicated re- quest for service interrupt (drqin/intrqin, drqout/intrqout). the external host can program, under user defined protocol, thresholds into the fifo input and output threshold sfrs which determine when the fifo request for service interrupt is generated to the host cpu. the fifo module external host interface is configured by the internal cpu via the mode sfr. ``the external host can enable and disable host interface interrupts via the host control sfr.'' data stream commands in the input fifo channel allow the host to influence the processing of data blocks and are sent with the data flow to maintain synchronization. data stream commands in the output fifo channel allow the internal cpu to per- form the same function, and also to set the output fifo request service status logic to the host cpu regardless of the programmed value in the thresh- old sfr. slave interface address decoding the upi-452 determines the desired host function through address decoding. the lower three bits of the address as well as the read, write, chip se- lect (cs ) and dma acknowledge (dack ) are used for decoding. table 3 shows the pin states and the read or write operations associated with each con- figuration. interrupts to the host the upi-452 interrupts the external host via the intrq pin. in addition, the drqin and drqout pins can be multiplexed as interrupt request lines, intrqin and intrqout respectively, when dma is disabled. this provides two special fifo ``re- quest for service'' interrupts. there are eight fifo-related interrupt sources; two from the input fifo; three from the output fifo; one from the immediate command out sfr; one from the immediate command in sfr; and one due to fifo dma freeze mode. input fifo: the input fifo interrupt is generated whenever: a. the input fifo contains space for a threshold number of bytes. 22
upi-452 table 3. upi-452 address decoding dack cs a2 a1 a0 read write 1 1 x x x no operation no operation 1 0 0 0 0 data or dma from output fifo channel data or dma to input fifo channel 1 0 0 0 1 data stream command from output fifo channel data stream command to input fifo channel 1 0 0 1 0 host status sfr read reserved 1 0 0 1 1 host control sfr read host control sfr write 1 0 1 0 0 immediate command sfr read immediate command to sfr write 1 0 1 1 x reserved reserved 0 x x x x dma data from output fifo channel dma data to input fifo channel 1 0 1 0 1 reserved reserved notes: 1. attempting to read a dsc as a data byte will result in invalid data being read. the read pointers are not incremented so that the dsc is not lost. attempting to read a data byte as a dsc has the same result. 2. if dack is active the upi-452 will attempt a dma operation when rd or wr becomes active regardless of the dma enable bit (md6) in the mode sfr. care should be taken when using dack . for proper operation, dack must be driven high ( a 5v) when not using dma. b. when an input fifo overrun error condition ex- ists. the appropriate bits in the host status sfr are set and the interrupt is generated only if en- abled. output fifo: the output fifo request for serv- ice interrupt operates in a similar manner as the in- put fifo interrupt: a. when the fifo contains the threshold number of bytes or more. b. output fifo error condition interrupts are gener- ated when the output fifo is underrun. c. data stream command present in the output buffer latch. a data stream command interrupt is used to halt normal processing, using the command as a vector to a service routine. when dma is disabled, the user may program (through hc1) intrq to include fifo request for service interrupts or use intrqin and intrqout as request for service interrupts. immediate command interrupts: a. an immediate command out interrupt is generat- ed, if enabled, to the host and the corresponding host status sfr bit (hstat hst6) is cleared, when the internal cpu writes to the immediate command out (imout) sfr. when the host reads the immediate command out (imout) sfr the corresponding bit in the host status (hstat) sfr is set. this causes the slave status immediate command out status bit (sstat sst6) to be cleared indicating that the immediate command out (imout) sfr is empty. if en- abled, a fifo-slave interface will also be gener- ated to the internal cpu. (see figure 7b, immedi- ate command out flowchart.) b. an immediate command in interrupt is generat- ed, if enabled, to the host when the internal cpu has read a byte from the immediate command in (imin) sfr. the read operation clears the host status sfr immediate command in status bit (hstat hst2) indicating that the immediate command in sfr is empty. the corresponding slave status (sstat) sfr bit is also set to indi- cate an empty status. setting the slave status sfr bit generates a fifo-slave interface inter- rupt, if enabled, to the internal cpu. (see figure 7a, immediate command in flowchart.) note: immediate command in and out interrupts are ac- tually specific request for service interrupts to the host. fifo dma freeze mode: when the internal cpu invokes fifo dma freeze mode, for example at re- set or to reconfigure the fifo interface, intrq is activated. the intrq can only be deactivated by the external host reading the host status sfr (hst1 remains active until fifo dma freeze mode is disabled by the internal cpu). once an interrupt is generated, intrq will remain high until no interrupt generating condition exists. for a fifo underrun/overrun error interrupt, the in- terrupt condition is deactivated by the external host reading the host status sfr. an interrupt is serv- iced by reading the host status sfr to determine the source of the interrupt and vectoring the appro- priate service routine. 23
upi-452 dma requests to the host the upi-452 generates two dma requests, drqin and drqout, to facilitate data transfer between the host and the input and output fifo channels. a dma acknowledge, dack , is used as a chip select and initiates a data transfer. the external read and write signals select the input and output fifo re- spectively. the cs and address lines can also be used as a dma acknowledge for processors with onboard dma controllers which do not generate a dack signal. the internal cpu can configure the upi-452 to re- quest service from the external host via dma or in- terrupts by programming mode sfr md6 bit. in ad- dition the external host enables dma requests through bits 6 and 7 of the host control sfr. when a dma request is invoked the number of bytes trans- ferred to the input fifo is the total number of bytes in the input fifo (as determined by the cbp sfr) minus the value programmed in the input fifo threshold sfr. the dma request line is activated only when the input fifo has a threshold number of bytes that can be transferred. the output fifo dma request is activated when a dsc is written by the internal cpu at the end of a less than threshold size block of data (flush mode) or when the output fifo threshold is reached. the request remains active until the input fifo becomes full or the output fifo becomes empty. if a dsc is encountered during an output fifo dma transfer, the dma request is dropped until the dsc is read. the dma request will be reactivated after the dsc is read and remains active until the output fifo be- comes empty or another dsc is encountered. fifo module - internal cpu interface overview the input and output fifos are accessed by the internal cpu through direct addressing of the fifo in/command in and fifo out/command out special function registers. all of the 80c51 instruc- tions involving direct addressing may be used to ac- cess the fifo's sfrs. the fifo in, command in and immediate command in sfrs are actually read only registers, and their output counterparts are write only. internal dma transfers data between in- ternal memory, external memory and the special function registers. the special function registers appear as another group of dedicated memory ad- dresses and are programmed as the source or desti- nation via the dma0/dma1 source address or des- tination address special function registers. the fifo module manages the transfer of data between the external host and fifo sfrs. internal cpu access to fifo via software instructions the internal cpu has access to the input and out- put fifos via the fifo in/command in and fifo out/command out sfrs which reside in the special function register array. at the end of every instruction that involves a read of the fifo in/com- mand in sfr, the sfr is written over by a new byte from the input fifo channel when available. at the end of every instruction that involves a write to the fifo out/command out sfr, the new byte is written into the output fifo channel and the write pointer is incremented after the write operation (post incremented). the internal cpu reads the input fifo by using the fifo in/command in sfr as the source register in an instruction. those instructions which read the input fifo are listed below: add a,fifo in/command in addc a,fifo in/command in push fifo in/command in anl a,fifo in/command in orl a,fifo in/command in xrl a,fifo in/command in cjne a,fifo in/command in, rel subb a,fifo in/command in mov direct,fifo in/command in mov @ ri,fifo in/command in mov rn,fifo in/command in mov a,fifo in/command in after each access to these registers, they are over- written by a new byte from the fifo. note: instructions which use the fifo in or command in sfr as both a source and destination register will have the data destroyed as the next data byte is rewritten into the fifo in register at the end of the instruction. these instructions are not support- ed by the upi-452 fifo. data can only be read through the fifo in sfr and dscs through the command in sfr. data read through the com- mand in sfr will be read as 0ffh, and dscs read through the fifo in sfr will be read as offh. the immediate command in sfr is read with the same instructions as the fifo in and command in sfrs. 24
upi-452 the fifo in, command in and immediate com- mand in sfrs are read only registers. any write op- eration performed on these registers will be ignored and the fifo pointers will remain intact. the internal cpu uses the fifo out sfr to write to the output fifo and any instruction which uses the fifo out or command out sfr as a desti- nation will invoke a fifo write. dscs are differenti- ated from data by writing to the command out sfr. in the fifo, data stream commands have the ninth bit associated with the command byte set to ``1''. the instructions used to write to the output fifo are listed below: mov fifo out/commout, a mov fifo out/commout, direct mov fifo out/commout, rn pop fifo out/commout mov fifo out/commout, y data mov fifo out/commount, @ ri note: instructions which use the fifo out/command out sfrs as both a source and destination regis- ter cause invalid data to be written into the output fifo. these instructions are not supported by the upi-452 fifo. general purpose dma channels overview there are two identical general purpose dma chan- nels on the upi-452 which allow high speed data transfer from one writeable memory space to anoth- er. as many as 64k bytes can be transferred in a single dma operation. the following memory spaces can be used with dma channels: # internal data memory # external data memory # special function registers the special function register array appears as a limited group of dedicated memory addresses. the special function registers may be used in dma transfer operations by specifying the sfr as the source or destination address. the special function registers which may be used in dma transfers are listed in table 4. table 4 also shows whether the sfr may be used as source or destination only, or both. the fifo can be accessed during dma by using the fifo in sfr as the dma source address register (sar) or the fifo out sfr as the destination ad- dress register (dar). (note: since the fifo in sfr is a read only register, the dma transfer will be ig- nored if it is used as a dma dar. this is also true if the fifo out sfr is used as a dma sar.) each dma channel is software programmable to op- erate in either block mode or demand mode. in the block mode, dma transfers can be further pro- grammed to take place in burst mode or alternate cycle mode. in burst mode, the processor halts its execution and dedicates its resources to the dma transfer. in alternate cycle mode, dma cycles and instruction cycles occur alternately. in demand mode, a dma transfer occurs only when it is demanded. demands can be accepted from an external device (through external interrupt pins, ext0/ext1) or from either the serial channel or fifo flags. in this way, a dma transfer can be syn- chronized to an external device, the fifo or the se- rial port. if the external interrupt is configured in edge mode, a single byte transfer occurs per tran- sition. the external interrupt itself will occur if en- abled. if the external interrupt is configured in level mode, dma transfers continue until the external in- terrupt request goes inactive or the byte count be- comes zero. the following flags activate demand mode transfers of one byte to/from the fifo or seri- al channel: ri - serial channel receiver buffer full ti - serial channel transmitter buffer empty architecture there are three 16 bit and one 8 bit special function registers associated with each dma channel. # the 16 bit source address sfr (sar) points to the source byte. # the 16 bit destination address sfr (dar) points to the destination. # the 16 bit byte count sfr (bcr) contains the number of bytes to be transferred and is decre- mented when a byte transfer is accomplished. # the dma control sfr (dcon) is eight bits wide and specifies the source memory space, destina- tion memory space and the mode of operation. in auto increment mode, the source address and/ or destination address is incremented when a byte is transferred. when a dma transfer is complete (bcr e 0), the done bit is set and a maskable interrupt is generated. the go bit must be set to start any dma transfer (also, the slave control sfr frz bit must be set to disable fifo dma freeze mode). the two dma channels are designated as dma0 and dma1, and their corresponding registers are suffixed by 0 or 1; e.g. sar0, dar1, etc. 25
upi-452 table 4. dma accessible special function registers sfr symbol address source destination either only only accumulator a/acc 0e0h y b register b 0f0h y fifo in fin 0eeh y command in cin 0efh y fifo out fout 0feh y command out cout 0ffh y serial data buffer sbuf 099h y port 0 p0 080h y port 1 p1 090h y port 2 p2 0a0h y port 3 p3 0b0h y port 4 p4 0c0h y dma special function registers dma control sfr: dcon0, dcon1 symbolic physical address address dcon0 das ida sas isa dm tm done go 092h dcon1 das ida sas isa dm tm done go 093h (msb) (lsb) reset status: dcon0 and dcon1 e 00h bit definition: das ida destination address space 0 0 external data memory without auto-increment 0 1 external data memory with auto-increment 1 0 special function register 1 1 internal data memory sas isa source address space 0 0 external data memory without auto-increment 0 1 external data memory with auto-increment 1 0 special function register 1 1 internal data memory dm tm dma transfer mode 0 0 alternate-cycle transfer mode 0 1 burst transfer mode 1 0 fifo or serial channel demand mode 1 1 external demand mode 26
upi-452 done dma transfer flag: 0 dma transfer is not completed. 1 dma transfer is complete. note: this flag is set when contents of the byte count sfr decrements to zero. it is reset automatically when the dma vectors to its interrupt routine. go enable dma transfer: 0 disable dma transfer (in all modes). 1 enable dma transfer. if the dma is in the block mode, start dma transfer if possible. if it is in the demand mode, enable the channel and wait for a de- mand. note: the go bit is reset when the bcr decrements to zero. dma transfer modes the following four modes of dma operation are pos- sible in the upi-452. 1. alternate-cycle mode general alternate cycle mode is useful when cpu process- ing must occur during the dma transfers. in this mode, a dma cycle and an instruction cycle occur alternately. the interrupt request is generated (if en- abled) at the end of the process, i.e. when bcr dec- rements to zero. the transfer is initiated by setting the go bit in the dcon sfr. alternate-cycle fifo demand mode alternate cycle demand mode is useful for fifo transfers of a less urgent nature. as mentioned be- fore, cpu instruction cycles are interleaved with dma transfer cycles, allowing true parallel process- ing. this mode differs from fifo demand mode in that cpu instruction cycles must be interleaved with dma transfers, even if the fifo is demanding dma. in fifo demand mode, cpu cycles would never oc- cur if the fifo demand was present. input channel the dma is configured as in fifo demand mode and transfers are initiated whenever an input fifo service request is generated. dma transfer cycles are alternated with instruction execution cycles. dma transfers are terminated as in fifo demand mode. output channel the dma is configured as in fifo demand mode and transfers are initiated whenever an output fifo requests service. dma transfer cycles are alternated with instruction execution cycles. dma transfers are terminated as in fifo demand mode. the fifo logic resets the interrupt flag after trans- ferring the byte, so the interrupt is never generated. once the dma is programmed to service the fifo, the request for service interrupt for the fifo is inhib- ited until the dma is done (bcr e 0). 2. burst mode in burst mode the dma is initiated by setting the go bit in the dcon sfr. the dma operation con- tinues until bcr decrements to zero (zero byte count), then an interrupt is generated (if enabled). no interrupts are recognized during this dma opera- tion once it has started. input channel the fifo input channel can be used in burst mode by specifying the fifo in sfr as the dma source address. dma transfers begin when the go bit in the dma control sfr is set. the number of bytes to be transferred must be specified in the byte count sfr (bcr) and auto-incrementing of the sar must be disabled. once the go bit is set nothing can in- terrupt the transfer of data until the bcr is zero. in this mode, a data stream command encountered in the fifo will be held in the command in sfr with the pointers frozen, and invalid data (ffh) will be read through the fifo in sfr. if the input fifo becomes empty during the block transfer, an 0ffh will be read until bcr decrements to zero. output channel the output fifo channel can be used in burst mode by specifying the fifo out or command out sfr as the dma destination address. dma transfers begin when the go bit is set. this mode can be used to send a block of data or a block of data stream commands. if the fifo becomes full during the block transfer, the remaining data will be lost. 27
upi-452 note: all interrupts including fifo interrupts are not rec- ognized in burst mode. burst mode transfers should be used to service the fifo only when the user is certain that no data stream commands are in the block to be transferred (input fifo) and that the fifo contains enough space to store the block to be transferred. in all other cases alternate cycle or demand mode should be used. 3. fifo and serial channel demand modes notes: 1. if the output fifo is configured as a one byte buffer and the user program consists of two-cycle instructions only, then alternate-cycle mode should be used. 2. in non-auto increment mode for internal to exter- nal, or external to internal transfers, the lower 8 bits of the external address should not correspond to the fifo or serial port address. fifo demand mode although any dma mode is possible using the fifo buffer, only fifo demand and alternate cycle fifo demand modes are recommended. fifo demand mode dma transfers using the input fifo channel are set-up by setting the go bit and specifying the fifo in register as the dma source address regis- ter. the bcr should be set to the maximum number of expected transfers. the user must also program bit 1 of the slave control register (sc1) to deter- mine whether the slave status (sstat) sfr fifo request for service flag will be activated when the fifo becomes not empty or full. once the request for service flag is activated by the fifo, the dma transfer begins, and continues until the request flag is deactivated. while the request is active, nothing can interrupt the dma (i.e. it behaves like burst mode). the dma request is held active until one of the following occurs: 1) the fifo becomes empty. 2) a data stream command is encountered (this generates a fifo interrupt and dma operation resumes after the data stream command is read). 3) bcr e 0 (this generates a dma interrupt and sets the done bit). dma transfers to the output fifo channel are simi- lar. the fifo out or command out sfr is the dma destination address sfr and a transfer is started by setting the go bit. the user programs bit 0 of the slave control sfr (sc0) to determine whether a demand occurs when the output fifo is not full or empty. dma transfers begin when the request for service flag is activated by the fifo logic and continue as long as the flag is active. the flag remains active until one of the following occurs: 1) the fifo becomes full 2) bcr e 0 (this generates a dma interrupt and sets the done bit). as in alternate cycle fifo demand mode, the fifo logic resets the interrupt flag after transferring the byte, so the interrupt is never generated. after the go bit is set, the dma is activated if one of the following conditions takes place: sar(0/1) e fifo in and hifrs flag is set dar(0/1) e fifo out and hofrs flag is set the hifrs and hofrs signals are internal flags which are not accessible by software. these flags are similar to the sst0 and sst4 flags in the slave status register except that they are of the opposite polarity and once set they are not cleared until the input fifo becomes empty (hifrs) or the output fifo becomes full (hofrs). serial channel demand mode serial channel demand mode is the logical choice when using the serial port. the dmas can be acti- vated by one of the serial channel flags. receiver interrupt (ri) or transmitter interrupt (ti). sar(0/1) e sbuf and ri flag is set dar(0/1) e sbuf and ti flag is set note: ti flag must be set by software to initiate the first transfer. when the dma transfer begins, only one byte is transferred at a time. the serial port hardware auto- matically resets the flag after completion of the transfer, so an interrupt will not be generated unless dma servicing is held off due to the dma being done (bcr e 0) or when the hold/hold acknowl- edge logic is used and the dma does not own the bus. in this case a serial port interrupt may be gen- erated if enabled because of the status of the ri or ti flags. in fifo demand mode, alternate cycle fifo de- mand mode or serial port demand mode only one of the following registers (sbuf, fin or fout) should be used as either the sar or dar registers to pre- vent undesired transfers. for example if sar0 e fin and dar0 e sbuf in demand mode, the dma transfer will start if either the hifrs or ti flags are set. 28
upi-452 4. external demand mode the dma can be initiated by an external device via external interrupt 0 and 1 (int0/int1) pins. the int0 pin demands dma0 (channel 0) and int1 de- mands dma1 (channel 1). if the interrupts are con- figured in edge mode, a single byte transfer is ac- complished for every request. interrupts also result (int0 and int1) after every byte transfer (if en- abled). if the interrupts are configured in level mode, the dma transfer continues until the request goes inactive or bcr e 0. in either case, a dma interrupt is generated (if enabled) when bcr e 0. the go bit must be set for the transfer to begin. external memory dma when transferring data to or from external memory via dma, the hold (hld) and hold-acknowl- edge (hlda) signals are used for handshaking. the hold and hold-acknowledge are active low signals which arbitrate control of the local bus. the upi-452 can be used in a system where multi- masters are connected to a single parallel address/ data bus. the hld/hlda signals are used to share resources (memory, peripherals, etc.) among all the processors on the local bus. the upi-452 can be configured in any of three different external memory modes controlled by bits 5 and 6 (req & arb) in the pcon sfr (table 5). each mode is described below: requester mode: in this mode, the upi-452 is not the bus master, but must request the bus from another device. the upi-452 configures port pin p1.5 as a hld output and pin p1.6 as a hlda input. the upi-452 issues a hld signal when it needs ex- ternal access for a dma channel. it uses the local bus after receiving the hlda signal from the bus master, and will not release the bus until its dma operation is complete. arbiter mode: in this mode, the upi-452 is the bus master. it configures port pin p1.5 as hld input and pin p1.6 as hlda output. when a device as- serts the hld signal to use the local bus, the upi- 452 asserts the hlda signal after current instruction execution is complete. if the upi-452 needs an ex- ternal access via a dma channel, it waits until the requester releases the bus, hld goes inactive. disable mode: when external program memory is accessed by an instruction or by program counter overflow beyond the internal rom address or exter- nal data memory is accessed by movx instructions, it is a local memory access and the hld/hlda logic is not initiated. when a dma channel attempts data transfer to/from the external data memory, the hld/hlda logic is initiated as described below. dma transfers from the internal memory space to the internal memory space does not initiate the hld/hlda logic. the balance of the pcon sfr bits are described in the ``80c51 register description: power control sfr'' section below. latency when the go bit is set, the upi-452 finishes the current instruction before starting the dma opera- tion. thus the maximum latency is 3.5 microseconds (at 14 mhz). dma interrupt vectors each dma channel has a unique vectored interrupt associated with it. there are two vectored interrupts associated with the two dma channels. the dma interrupts are enabled and priorities set via the inter- rupt enable and priority sfr (see ``interrupts'' sec- tion). the interrupt priority scheme is similar to the scheme in 80c51. table 5. dma mode control - pcon sfr symbolic physical address address pcon e * arb req e * e * e * e * e * 87h (msb) (lsb) * defined as per mls-51 data sheet reset status: 00h definition: arb req 0 0 hld/hlda logic is disabled. 0 1 the upi-452 is in the requester mode. 1 0 the upi-452 is in the arbiter mode. 1 1 invalid 29
upi-452 when a dma operation is complete (bcr decre- ments to zero), the done flag in the respective dcon (dcon0 or dcon1) sfr is set. if the dma interrupt is enabled, the done flag is reset automat- ically upon vectoring to the interrupt routine. interrupts when dma is active if a burst mode dma transfer is in progress, the in- terrupts are not serviced until the dma transfer is complete. this is also true for level activated exter- nal demand dma transfers. during alternate cycle dma transfers, however, the interrupts are serviced at the end of the dma cycle. after that, dma cycles and instruction execution cycles occur alternately. in the case of edge activated external demand mode dma transfers, the interrupt is serviced at the end of dma transfer of that single byte. dma arbitration only one of the two dma channels is active at a time, except when both are configured in the alter- nate cycle mode. in this case, the dma cycles and instruction execution cycles occur in the following order: 1. dma cycle 0. 2. instruction execution. 3. dma cycle 1. 4. instruction execution. dma0 has priority over dma1 during simultaneous activation of the two dma channels. if one dma channel is active, the other dma channel, if activat- ed, waits until the first one is complete. if dma0 is already in the alternate cycle mode and dma1 is activated in alternate cycle mode, it will take two instruction cycles before dma1 is activated (due to the priority of dma0). once dma1 becomes active, the execution will follow the normal se- quence. if dma0 is already in the alternate cycle mode and dma1 is activated in burst mode, the dma1 burst transfer will follow the dma0 alternate cycle trans- fer (after the completion of the next instruction). if the upi-452 (as a requester) asserts a hld signal to request a dma transfer (see ``external memory dma'')and its other dma channel requests a trans- fer before the hlda signal is received, the channel having higher priority is activated first. a burst mode transfer on channel 0 can not be interrupted since dma0 has the highest priority. a demand mode transfer on channel 0 is the only type of activity that can interrupt a block transfer on dma1. if, while executing a dma transfer, the arbiter re- ceives a hld signal, and then before it can acknowl- edge, its other dma channel requests a transfer, it then completes the second dma transfer before sending the hlda signal to release the bus to the hld request. dma transfers may be held off under the following conditions: 1. a write to any of the dma registers inhibits the dma for one instruction cycle. note: an instruction cycle may be executed in 1, 2 or 4 machine cycles dependent on the instruction being executed. dma transfers are only executed after the completion of an instruction cycle never be- tween machine cycles of a single instruction cycle. similarly instruction cycles are only executed upon completion of a dma transfer whether it be a one machine cycle transfer or two machine cycles (for ext. to ext. memory transfers). 2. a single machine cycle dma register read opera- tion (i.e. mov a, dcon0) will inhibit the dma for one instruction cycle. however a two cycle dma register read operation will not inhibit the dma (i.e. mov p1, dcon0). if the hold/hold acknowledge logic is enabled in requestor mode the hold request will go active once the go bit has been set (for burst mode) and once the demand flag is set (for demand mode) regard- less of whether the dma is held off by one of the above conditions. the dma transfer waveforms are in figures 8-11. 30
upi-452 231428 13 figure 8. dma transfer from external memory to external memory 231428 14 figure 9. dma transfer from external memory to internal memory 231428 15 figure 10. dma transfer from internal memory to external memory 31
upi-452 231428 16 figure 11. dma transfer from internal memory to internal memory internal interrupts overview the upi-452 provides a total of eight interrupt sourc- es (table 6). their operation is the same as in the 80c51, with the addition of three new interrupt sources for the upi-452 fifo and dma features. these added interrupts have their enable and priori- ty bits in the interrupt enable and priority (iep) sfr. the iep sfr is in addition to the 80c51 interrupt enable (ie) and interrupt priority (ip) sfrs. the add- ed interrupt sources are also globally enabled or dis- abled by the ea bit in the interrupt enable sfr. ta- ble 6 lists the eight interrupt sources in order of pri- ority. table 7 lists the eight interrupt sources and their respective address vector location in program memory. (dma interrupts are discussed in the ``gen- eral purpose dma channels'' section. additional in- terrupt information for timer/counter, serial chan- nel, external interrupt may be found in the microcon- troller handbook for the 80c51.) fifo module interrupts to internal cpu the fifo module generates interrupts to the inter- nal cpu whenever the fifo requests service or when a data stream command is in the command in sfr. the input fifo will request service whenev- er it becomes full or not empty depending on bit 1 of the slave control sfr (ifrs). similarly, the output table 6. interrupt priority interrupt source priority level (highest) external interrupt 0 0 internal timer/counter 0 1 dma channel 0 request 2 external interrupt 1 3 dma channel 1 request 4 internal timer/counter 1 5 fifo - slave bus interface 6 serial channel 7 (lowest) table 7. interrupt vector addresses interrupt source starting address external interrupt 0 3 (003h) internal timer/counter 0 11 (00bh) external interrupt 1 19 (013h) internal timer/counter 1 27 (01bh) serial channel 35 (023h) fifo - slave bus interface 43 (02bh) dma channel 0 request 51 (033h) dma channel 1 request 59 (03bh) fifo requests service when it becomes empty or not full as determined by bit 0 of the slave control sfr (ofrs). request for service interrupts are generated only if enabled by the internal cpu via the interrupt enable sfr, and the slave control regis- ter. 32
upi-452 a data stream command interrupt is generated whenever there is a data stream command in the command in sfr. the interrupt is generated to ensure that the internal interrupt is recognized be- fore another instruction is executed. immediate command interrupts a. an immediate command in interrupt is generat- ed, if enabled, to the internal cpu when the host has written to the immediate command in (imin) sfr. the write operation clears the slave status sfr bit (sstat sst2) and sets the host status sfr bit (hstat hst2) to indicate that a byte is present in the immediate command in sfr. when the internal cpu reads the immediate com- mand in (imin) sfr the slave status sfr status bit is set, and the host status sfr status bit is cleared indicating the imin sfr is empty. clear- ing the host status sfr bit will cause a request for service (intrq) interrupt, if enabled, to signal the host that the imin sfr is empty. (see figure 7a, immediate command in flowchart.) b. an immediate command out interrupt is gener- ated, if enabled, to the internal cpu when the host has read the immediate command out sfr. the host read causes the slave status immediate command out bit (sstat sst6) to be set and the corresponding host status bit (hstat hst6) to be cleared indicating the sfr is empty. when the internal cpu writes to the imme- diate command out sfr, the host status bit is set and slave status bit is cleared to indicate the sfr is full. (see figure 7b, immediate command out flowchart.) note: immediate command in and out interrupts are ac- tually specific fifo-slave interface interrupts to the internal cpu. one instruction from the main program is executed between two consecutive interrupt service routines as in the 80c51. however, if the second interrupt service routine is due to a data stream command interrupt, the main program instruction is not execut- ed (to prevent misreading of invalid data). interrupt enabling and priority each of the three interrupt special function registers (ie, ip and iep) is listed below with its corresponding bit definitions. interrupt enable sfr (ie) symbolic physical address address ie ea e e es et1 ex1 et0 ex0 0a8h (msb) (lsb) symbol position function ea ie.7 enables all interrupts. if ea e 0, no interrupt will be acknowledged. if ea e 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. e ie.6 (reserved) e ie.5 (reserved) es ie.4 serial channel interrupt enable et1 ie.3 internal timer/counter 1 overflow interrupt ex1 ie.2 external interrupt request 1. et0 ie.1 internal timer/counter 0 overflow interrupt ex0 ie.0 external interrupt request 0. 33
upi-452 interrupt priority sfr (ip) a priority level of 0 or 1 may be assigned to each interrupt source, with 1 being higher priority level, through the ip and the iep (interrupt enable and priority) sfr. a priority level of 1 interrupt can interrupt a priority level 0 service routine to allow nesting of interrupts. symbolic physical address address ip e e e ps pt1 px1 pt0 px0 0b8h (msb) (lsb) symbol position function priority within a level (lowest) e ip.7 (reserved) e e ip.6 (reserved) e e ip.5 (reserved) e ps ip.4 local serial channel 0.7 pt1 ip.3 internal timer/counter 1 0.5 px1 ip.2 external interrupt request 1 0.3 pt0 ip.1 internal timer/counter 0 0.1 px0 ip.0 external interrupt request 0 0.0 (highest) interrupt enable and priority sfr (iep) the interrupt enable and priority register establishes the enabling and priority of those resources not covered in the interrupt enable and interrupt priority sfrs. symbolic physical address address iep e e pfifo edma0 edma1 pdma0 pdma1 efifo 0f8h (msb) (lsb) priority symbol position function within a level e iep.7 (reserved) e iep.6 (reserved) pfifo iep.5 fifo slave bus interface interrupt priority 0.6 edma0 iep.4 dma channel 0 interrupt enable edma1 iep.3 dma channel 1 interrupt enable pdma0 iep.2 dma channel 0 priority 0.2 pdma1 iep.1 dma channel 1 priority 0.4 efifo iep.0 fifo slave bus interface interrupt enable 34
upi-452 fifo-external host interface fifo dma freeze mode overview during fifo dma freeze mode the internal cpu can reconfigure the fifo interface. fifo dma freeze mode is provided to prevent the host from accessing the fifo during a reconfiguration se- quence. the internal cpu invokes fifo dma freeze mode by clearing bit 3 of the slave control sfr (sc3). intrq becomes active whenever fifo dma freeze mode is invoked to indicate the freeze status. the interrupt can only be deactivated by the host reading the host status sfr. during fifo dma freeze mode only two operations are possible by the host to the upi-452 slave, the balance are disabled, as shown in table 8. the in- ternal dma is disabled during fifo dma freeze mode, and the internal cpu has write access to all of the fifo control sfrs (table 9). initialization at power on reset the fifo host interface is auto- matically frozen. the slave control enable fifo dma freeze mode bit defaults to fifo dma freeze mode (slcon frz e 0). below is a list of the fifo special function registers and their default power on reset values; sfr name label value channel boundary pointer cbp 40h / 64d output channel read pointers orpr 40h / 64d output channel write pointers owpr 40h / 64d input channel read pointers irpr 00h / 00d input channel write pointers iwpr 00h / 00d input threshold ithr 80h / 128d output threshold othr 01h / 1d the input and output fifo channels can be recon- figured by programming any of these sfrs while the upi-452 is in the freeze mode. the host is notified when the freeze mode is active by a ``1'' in hst1 of the host status register (hstat). the host should interrogate hst1 to determine the status of the fifo interface following reset before attempting to read from or write to the upi-452 fifo buffer. note: during the initialization sequence of the upi-452 fifo sfrs, the othr should be changed from the default setting of 1 to a value between 2 and (80h-cbp)-1 . please refer to the section on input and output fifo threshold sfrs for further infor- mation. table 8. slave bus interface status during fifo dma freeze mode interface pins; cs a2 a1 a0 read write operation in status in dack normal mode fifo dma freeze mode 1 0 0 1 0 0 1 read host status sfr operational 1 0 0 1 1 0 1 read host control sfr operational 1 0 0 1 1 1 0 write host control sfr disabled 1 0 0 0 0 0 1 data or dma data from disabled output channel 1 0 0 0 0 1 0 data or dma data to disabled input channel 1 0 0 0 1 0 1 data stream command from disabled output channel 1 0 0 0 1 1 0 data stream command to disabled input channel 1 0 1 0 0 0 1 read immediate command disabled out from output channel 1 0 1 0 0 1 0 write immediate command disabled in to input channel 0 x x x x 0 1 dma data from output disabled channel 0 x x x x 1 0 dma data to input channel disabled 35
upi-452 the upi-452 can also be programmed to interrupt the host following power on reset in order to indi- cate to the host that fifo dma freeze mode is in progress. this is done by enabling the intrq inter- rupt output pin via the mode sfr (md4) before the slave control sfr enable fifo dma freeze mode bit is set to normal mode. at power on reset the mode sfr is forced to zero. this disables all inter- rupt and dma output pins (intrq, drqin/ intrqin and drqout/intrqout). because the host status sfr fifo dma freeze mode in prog- ress bit is set, a request for service, intrq, inter- rupt is pending until the host status sfr is read. this is because the fifo dma freeze mode inter- rupt is always enabled. if the slave control fifo dma freeze mode bit (slcon frz) is set to nor- mal mode before the mode sfr intrq bit is en- abled, the intrq output will not go active when the mode sfr intrq bit is enabled if the host status sfr has been read. the default values for the fifo and slave interface represents minimum upi-452 internal initialization. no specific special function register initialization is required to begin operation of the fifo slave inter- face. the last initialization instruction must always set the upi-452 to normal mode. this causes the upi-452 to exit fifo dma freeze mode and en- ables host read/write access of the fifo. following reset, either hardware (via the rst pin) or software (via hcon sfr bit hc3) the upi-452 re- quires 2 internal machine cycles (24 tclcl) to up- date all internal registers. invoking fifo dma freeze mode during normal operation when the upi-452 is in normal operation, fifo dma freeze mode should not be arbitrarily invoked by clearing sc3 (sc3 e 0) because the external host runs asynchronously to the internal cpu. invoking fifo dma freeze mode without first stopping the external host from accessing the upi-452 will not guarantee a clean break with the external host. the proper way to invoke fifo dma freeze mode is by issuing an immediate command to the external host indicating that fifo dma freeze mode will be invoked. upon receiving the immediate command, the external host should complete servicing all pending interrupts and dma requests, then send an immediate command back to the upi-452 acknowl- edging the fifo dma freeze mode request. after issuing the first immediate command, the internal cpu should not perform any action on the fifo until fifo dma freeze mode is invoked. if fifo dma freeze mode is invoked without stop- ping the host during host transfers, only the last two bytes of data written into or read from the fifo will be valid. the timing diagram for disabling the fifo module to the external host interface is illustrated in figure 12. due to this synchronization sequence, the upi-452 might not go into fifo dma freeze mode immediately after sc3 is cleared. a special bit in the slave status register (sst5) is provided to indicate the status of the fifo dma freeze mode. the fifo dma freeze mode operations described in this sec- tion are only valid after sst5 is cleared. as fifo dma freeze mode is invoked, the drqin or drqout will be deactivated (stopping the trans- ferring of data), bit 1 of the host status sfr will be set (hst1 e 1), and sst5 will be cleared (sst5 e 0) to indicate to the external host and internal cpu that the slave interface has been frozen. after the freeze becomes effective, any attempt by the exter- nal host to access the fifo will cause the overrun and underrun bits to be activated (bits hst7 (for reads) or hst3 (for writes)). these two bits, hst3 and hst7, will be set (deactivated) after the host status sfr has been read. if intrq is used to re- quest service, the fifo interface is frozen upon completion of any host read or write operation in progress. 231428 17 figure 12. disabling fifo to host slave interface timing diagram 36
upi-452 external host writing to the immediate command in sfr and the host control sfr is also inhibited when the slave bus interface is frozen. writing to these two registers after fifo dma freeze mode is invoked will also cause hst3 (overrun) to be activat- ed (hst3 e 0). similarly, reading the immediate command out register by the external host is dis- abled during fifo dma freeze mode, and any at- tempt to do so will cause the clearing (deactivating, ``0'') of hst7 bit (underrun). after the slave bus interface is frozen, the internal cpu can perform the following operations on the fifo special function registers (these operations are allowed only during fifo dma freeze mode). for fifo 1. changing the channel reconfiguration boundary pointer sfr. 2. changing the input and output threshold sfr. to enhance the 3. writing to the read and write testability pointers of the input and output fifo's. 4. writing to and reading the host control sfrs. 5. controlling some bits of host and slave status sfrs. 6. reading the immediate command out sfr and writing to the immediate comand in sfr. description of each of these special functions are as follows: fifo module sfrs during fifo dma freeze mode table 9 summarizes the characteristics of all the fifo special function registers during normal and fifo dma freeze modes. the registers that require special treatment in fifo dma freeze mode are: hcon, iwpr, irpr, owpr, orpr, hstat, sstat, min & mout sfrs. they can be described in detail as follows: host control sfr (hcon) during normal operation, this register is written to or read by the external host. however, in fifo dma freeze mode (i.e. sst5 e 0) the upi-452 internal cpu has write access to the host control sfr and write operations to this sfr by the external host will not be accepted. if the host attempts to write to hcon, the input channel error condition flag (hst3) will be cleared. input fifo pointer registers (irpr & iwpr) once the fifo module is in fifo dma freeze mode, error flags due to overrun and underrun of the input fifo pointers will be disabled. any attempt to create an overrun or underrun condition by changing the input fifo pointers would result in an inconsist- ency in performance between the status flag and the threshold counter. to enhance the speed of the upi-452, read opera- tions on the input fifo will look ahead by two bytes. hence, every time the irpr is changed during fifo dma freeze mode, two nops need to be executed so that the two byte pipeline can be updated with the new data bytes pointed to by the new irpr. the threshold counter sfr also needs to change by the same number of bytes as the irpr (increase threshold counter if irpr goes forward or decrease if irpr goes backward). this will ensure that future interrupts will still be generated only after a thresh- old number of bytes are available. (see ``input and output fifo threshold sfr'' section below.) in fifo dma freeze mode, the internal cpu can also change the content of iwpr, and each change of iwpr also requires an update of the threshold counter sfr. normally, the internal cpu cannot write into the in- put fifo. it can, however, during fifo dma freeze mode by first reconfiguring the fifo as an output fifo (refer to ``input and output fifo threshold sfr'' section below). changing the irpr to be equal to iwpr generates an empty condition while changing iwpr to be equal to irpr generates a full condition. the order in which the pointers are written determines whether a full or empty condition is gen- erated. output fifo pointer sfr (orpr and owpr) in fifo dma freeze mode the contents of owpr can be changed by the internal cpu, but each change of owpr or orpr requires the threshold counter sfr to be updated as described in the next section. a nop must be executed whenever a new value is written into orpr, as just described for changes to irpr. as before, changing orpr to be equal to owpr will generate an empty condition, output fifo overrun or underrun condition cannot be generated though. the fifo pointers should not be set to a value outside of its range. 37
upi-452 table 9. fifo sfr's characteristics during fifo dma freeze mode normal fifo dma freeze mode label name operation operation (sst5 e 1) (sst5 e 0) hcon host control not accessible read & write hstat host status read only read & write 4 slcon slave control read & write read & write sstat slave status read only read & write 4 iep interrupt enable & priority read & write read & write mode mode register read & write read & write iwpr input fifo write pointer read only read & write 5 irpr input fifo read pointer read only read & write 1, 5 owpr output fifo write pointer read only read & write 6 orpr output fifo read pointer read only read & write 2, 6 cbp channel boundary pointer read only read & write 3 imin immediate command in read only read & write imout immediate command out read & write read & write fin fifo in read only read only cin command in read only read only fout fifo out read & write read & write cout command out read & write read & write ithr input fifo threshold read only read & write othr output fifo threshold read only read & write notes: 1. writing of irpr will automatically cause the fifo in sfr to load the contents of the input fifo from that location. 2. writing to orpr will automatically cause the iobl sfr to load the contents of the output fifo at that orpr address. 3. writing to the cbp sfr will cause automatic reset of the four pointers of the input and output fifo channels. 4. the internal cpu cannot directly change the status of these registers. however, by changing the status of the fifo channels, the internal cpu can indirectly change the contents of the status registers. 5. changing the input fifo read/write pointers also requires that a consistent update of the input fifo threshold counter sfr. 6. changing the output fifo read/write pointers also requires that a consistent update of the output fifo threshold counter sfr. 38
upi-452 input and output fifo threshold sfr (ithr & othr) the input and output fifo threshold sfrs are also programmable by the internal cpu during fifo dma freeze mode. for proper operation of the threshold feature, the threshold sfr should be changed only when the input and output fifo channels are emp- ty, since they reflect the current number of bytes available to read/write before an interrupt is gener- ated. table 10 illustrates the threshold sfrs range of values and the number of bytes to be transferred when the request for service flag is activated: table 10. threshold sfrs range of values and number of bytes to be transferred ithr no. of bytes othr no. of bytes (lower available to (lower available to seven bits) be written seven bits) be read 0 cbp 2 3 1 cbp-1 3 4 2 cbp-2 ## #### #### ## (80h-cbp)-3 (80h-cbp)-2 cbp-3 3 (80h-cbp)-2 (80h-cbp)-1 (80h-cbp)-1 (80h-cbp) the eighth bit of the input and output fifo thresh- old sfr indicates the status of the service requests regardless of the freeze condition. if the eighth bit is a ``1'', the fifo is requesting service from the exter- nal host. in other words, when the threshold sfr value goes below zero (2's complement), a service request is generated * . * the 8th bit of the ithr sfr must be set during initialization if the host interrupt request is desired immediately upon leaving freeze mode. normally the ithr sfr is decremented after each external host write to the input fifo and incre- mented after each internal cpu read of the input fifo. the othr sfr is decremented by internal cpu writes and incremented by external host reads. thus if the pointers are moved when the fifo's are not empty, these relationships can be used to calcu- late the offset for the threshold sfrs. it is best to change the threshold sfrs only when the fifo's are empty to avoid this complication. the threshold registers should also be updated after the pointers have been manipulated. note: the ithr should only be programmed in the range from 0 to (cbp-3). an ithr value of (cbp-2) could result in a failure to set the input fifo service re- quest signal after the input fifo has been emptied. correspondingly, the othr should be programmed in the range from 2 to (80h-cbp)-1 . an othr value of 1 could result in a failure to set the output fifo service request after subsequent writes by the upi-452 have filled the output fifo. note: when programming the ithr sfr, the eighth bit should be set to 1 (or'd with 80h). this causes hstat sfr hst0 e 0, input fifo request for service. if ithr bit 7 e 0 then hstat hst0 e 1, input fifo does not request service, and no in- terrupt will be generated. host status sfr (hstat) when in fifo dma freeze mode, some bits in the host status sfr are forced high and will not reflect the new status until the system returns to normal operation. the definition of the register in fifo dma freeze mode is as follows: note: the internal cpu reads this shadow latch value when reading the host status sfr. the shadow latch will keep the information for these bits so nor- mal operation can be resumed with the right status. the following bits are set ( e 1) when fifo dma freeze mode is invoked; hst7 output fifo error condition flag 1 e no error. 0 e an invalid read has been done on the output fifo or the immediate command out register by the host cpu. note: the normal underrun error condition status is dis- abled. if an immediate command out (imout) sfr read is attempted during fifo dma freeze mode, the contents of the imout sfr is output on the data buffer and the error status is cleared ( e 0). hst6 immediate command out sfr status during normal operation, this bit is cleared ( e 0) when the imout sfr is written by the upi-452 internal cpu and set ( e 1) when the imout sfr is read by the external host. once the host-slave interface is frozen (i.e. sst5 e 0), this bit will be read a sa1bythe host cpu. a shadow latch will keep the infor- mation for this bit so normal operation can be resumed with the correct status. shadow latch: 1 e internal cpu reads the imout sfr 0 e internal cpu writes to the imout sfr 39
upi-452 hst5 data stream command at output fifo this bit is forced to a ``1'' during fifo dma freeze mode to prevent the external host cpu from trying to read the dsc. once nor- mal operation is resumed, hst5 will reflect the data/command status of the current byte in the output fifo. shadow latch (read by the internal cpu): 1 e no data stream command (dsc) 0 e data stream command at output fifo hst4 output fifo service request status when fifo dma freeze mode is invoked, this bit no longer reflects the output fifo re- quest service status. this bit wll be forced to a ``1''. hst3 input fifo error condition flag 1 e no error. 0 e one of the following operations has been attempted by the external host and is invalid: 1) write into the input fifo 2) write into the host control sfr 3) write into the immediate command in sfr note: the normal input fifo overrun condition is dis- abled. hst2 immediate command in sfr status this bit is normally cleared when the internal cpu reads the imin sfr and set when the external host cpu writes into the imin sfr. when the host-slave interface is frozen, read- ing and writing of the imin by the internal cpu will change the shadow latch of this bit. this bit will be read as a ``1'' by the external host. shadow latch. 1 e internal cpu writes into imin sfr 0 e internal cpu reads the imin sfr hst1 fifo dma freeze mode status 1 e fifo dma freeze mode. 0 e normal operation (non-fifo dma freeze mode). note: this bit is used to indicate to the external host that the host-slave interface has been frozen and hence the external host functions are now reduced as shown in table 8. hst0 input fifo request service satus when slave interface is frozen this bit no longer reflects the input fifo request serv- ice status. this bit will be forced to a ``1''. slave status sfr (sstat) the slave status sfr is a read-only sfr. however, once the slave interface is frozen, most of the bits of this sfr can be changed by the internal cpu by reconfiguring the fifo and accessing the fifo spe- cial function registers. sst7 output fifo overrun error flag inoperative in fifo dma freeze mode. sst6 immediate command out sfr status in fifo dma freeze mode, this bit will be cleared when the internal cpu reads the im- mediate command out sfr and set when the internal cpu writes to the immediate command out register. sst5 fifo-external interface fifo dma freeze mode status this bit indicates to the internal cpu that fifo dma freeze mode is in progress and that it has write access to the fifo control, host control and immediate command sfrs. sst4 output fifo request service status during normal operation, this bit indicates to the internal cpu that the output fifo is ready for more data. the status of this bit re- flects the position of the output fifo read and write pointers. hence, in fifo dma freeze mode, this flag can be changed by the internal cpu indirectly as the read and write pointers change. sst3 input fifo underrun flag inoperative during fifo dma freeze mode. during normal operation, a read operation clears ( e 0) this bit when there are no data bytes in the input fifo and deactivated ( e 1) when the slave status sfr is read. in fifo dma freeze mode, this bit will not be cleared by an input fifo read underrun error condi- tion, nor will it be reset by the reading of the slave status sfr. sst2 immediate command in sfr status this bit is normally activated ( e 0) when the external host cpu writes into the immediate command in sfr and deactivated ( e 1) when it is read by the internal cpu. in fifo dma freeze mode, this bit will not be activat- ed ( e 0) by the external host's writing of the immediate command in sfr since this func- tion is disabled. however, this bit will be cleared ( e 0) if the internal cpu writes to the immediate command in sfr and it will be set e 1) if it reads from the register. 40
upi-452 sst1 data stream command at input fifo flag in fifo dma freeze mode, this bit operates normally. it indicates whether the next byte of data from the input fifo is a dsc or data byte. if it is a dsc byte, reading from the fifo in sfr will result in reading invalid data (ffh) and vice versa. in fifo dma freeze mode, this bit still reflects the type of data byte available from the input fifo. sst0 input fifo service request flag during normal operation, this bit is activated ( e 0) when the input fifo contains bytes that can be read by the internal cpu and deacti- vated ( e 1) when the input fifo does not need any service from the internal cpu. in fifo dma freeze mode, the status of this bit should not change unless the pointers of the input fifo are changed. in this mode, the in- ternal cpu can indirectly change this bit by changing the read and write pointers of the input fifo but cannot change it directly. immediate command in/out sfr (imin/imout) if fifo dma freeze mode is in progress, writing to the immediate command in sfr by the external host will be disabled, and any such attempt will cause hst3 to be cleared ( e 0). similarly, the imme- diate command out sfr read operation (by the host) will be disabled internally and read attempts will cause hst7 to be cleared ( e 0). internal cpu read and write of the fifo during fifo dma freeze mode in normal operation, the input fifo can only be read by the internal cpu and similarly, the output fifo can only be written by the internal cpu. during fifo dma freeze mode, the internal cpu can read the entire contents of the input fifo by programming the cbp sfr to 7fh, setting the irpr sfr to zero, and then the iwpr sfr to zero. programming the pointer registers in this order generates a fifo full signal to the fifo logic and enables internal cpu read operations. if the iwpr and irpr are already zero, the write pointer should be changed to a non- zero value to clear the empty status then the point- ers can be set to zero. writing to the irdr sfr automatically updates the look ahead registers. in a similar manner, the internal cpu can write to all 128 bytes of the fifo by setting the cbp sfr to zero, setting owpr sfr to zero, and then setting orpr sfr to zero. this generates a fifo empty signal and allows internal cpu write operations to all 128 bytes of the fifo. the threshold registers also need to be adjusted when the pointers are changed. (see ``input and output fifo threshold sfr'' sec- tion below.) memory organization the upi-452 has separate address spaces for pro- gram memory and data memory like the 80c51. the program memory can be up to 64k bytes. the lower 8k of program memory may reside on-chip. the data memory consists of 256 bytes of on-chip ram, up to 64k bytes of off-chip ram and a number of ``sfrs'' (special function registers) which appear as yet another set of unique memory addresses. table 11a. internal memory addressing memory space addressing method lower 128 bytes of direct or indirect internal ram upper 128 bytes indirect only of internal ram upi-452 sfr's direct only the 80c51 special function registers are listed in table 11a, and the additional upi-452 sfrs are list- ed in table 11b. a brief description of the 80c51 core sfrs is also provided below. accessing external memory as in the 80c51, accesses to external memory are of two types: accesses to external program memory and accesses to external data memory. external program memory is accessed under two conditions: 1) whenever signal ea e 0; or 2) whenever the program counter (pc) contains a number that is larger than 1fffh. this requires that the romless versions have ea wired low to enable the lower 8k program bytes to be fetched from external memory. external data memory is accessed using either the movx @ dptr (16 bit address) or the movx @ ri (8 bit address) instructions, or during external data memory transfers. 41
upi-452 table 11b. 80c51 special function registers symbol name address contents * acc accumulator 0e0h 00h * b b register 0f0h 00h * psw program status 0d0h 00h word sp stack pointer 81h 07h dptr data pointer 82h 0000h (consisting of dph and dpl) * p0 port 0 80h 0ffh * p1 port 1 90h 0ffh * p2 port 2 0a0h 0ffh * p3 port 3 0b0h 0ffh * ip interrupt priority 0b8h 0e0h control * ie interrupt enable 0a8h 60h control tmod timer/counter 89h 00h mode control * tcon timer/counter 88h 00h control th0 timer/counter 8ch 00h 0 (high byte) tl0 timer/counter 8ah 00h 0 (low byte) th1 timer/counter 8dh 00h 1 (high byte) tl1 timer/counter 8bh 00h 1 (low byte) * scon serial control 98h 00h sbuf serial data buff 99h i pcon power control 87h i0h i e indeterminate the sfrs marked with an asterisk ( * ) are both bit- and byte- addressable. the functions of the sfrs are as fol- lows: table 11c. upi-452 additional special function registers symbol name address contents bcrl0 dma byte 0e2h i count low byte/ bcrh0 high byte/ 0e3h i channel 0 bcrl1 low byte/ 0f2h i bcrh1 hi byte/ 0f3h i channel 1 cbp channel boundary 0ech 40h pointer cin command in 0efh i cout command out 0ffh i dma destination address table 11c. upi-452 additional special function registers (continued) symbol name address contents darl0 low byte/ 0c2h i darh0 hi byte/ 0c3h i channel 0 darl1 low byte/ 0d2h i darh1 hi byte/ 0d3h i channel 1 dcon0 dma0 control 92h 00h dcon1 dma1 control 93h 00h fin fifo in 0eeh i fout fifo out 0feh i hcon host control 0e7h 00h hstat host status 0e6h 0fbh * iep interrupt enable 0f8h 0c0h and priority imin immediate command 0fch i in imout immediate command 0fdh i out irpr input read 0ebh 00h pointer ithr input fifo 0f6h 80h threshold iwpr input write 0eah 00h pointer mode mode register 0f9h 8fh orpr output read 0fah 40h pointer othr output fifo 0f7h 01h threshold owpr output write 0fbh 40h threshold * p4 port 4 0c0h 0ffh dma source address sarl0 low byte/ 0a2h i sarh0 hi byte/ 0a3h i channel 0 sarl1 low byte/ 0b2h i sarh1 hi byte/ 0b3h i channel 1 * slcon slave control 0e8h 04h sstat slave status 0e9h 08fh i e indeterminate the sfrs marked with an asterisk ( * ) are both bit- and byte- addressable. the functions of the sfrs are as fol- lows: 42
upi-452 miscellaneous special function register description 80c51 sfrs accumulator acc is the accumuator sfr. the mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as a. b register the b sfr is used during multiply and divide opera- tions. for other instructions it can be treated as an- other scratch pad register. program status word the psw sfr contains program status information as detailed in table 12. stack pointer the stack pointer register is 8 bits wide. it is incre- mented before data is stored during push and call executions. while the stack may reside any- where in on-chip ram, the stack pointer is initialized to 07h after a reset. this causes the stack to begin at location 08h. data pointer the data pointer (dptr) consists of a high byte (dph) and a low byte (dpl). its intended function is to hold a 16-bit address. it may be manipulated as a 16-bit register or as two independent 8-bit registers. ports 0 to 4 p0, p1, p2, p3 and p4 are the sfr latches of ports 0, 1, 2, 3 and 4, respectively. serial data buffer the serial data buffer is actually two separate regis- ters, a transmit buffer and a receive buffer register. when data is moved to sbuf, it goes to the transmit buffer where it is held for serial transmission. (mov- ing a byte to sbuf is what initiates the transmis- sion.) when data is moved from sbuf, it comes from the receive buffer. timer/counter sfr register pairs (th0, tl0), and (th1, tl1) are the 16-bit counting registers for timer/counters 0 and 2. power control sfr (pcon) the pcon register (table 13) controls the power down and idle modes in the upi-452, as well as pro- viding the ability to double the serial channel baud rate. there are also two general purpose flag bits available to the user. bits 5 and 6 are used to set the hold/hold acknowledge mode (see ``general purpose dma channels'' section), and bit 4 is not used. 43
upi-452 table 12. program status word symbolic physical address address psw cy ac fo rs1 rs0 ov e p 0d0h (msb) (lsb) symbol position name cy psw.7 carry flag ac psw.6 auxiliary carry (for bcd operations) f0 psw.5 flag 0 (user assignable) rs1 psw.4 register bank select bit 1 * rs0 psw.3 register bank select bit 0 * ov psw.2 overflow flag e psw.1 (reserved) p psw.0 parity flag * (rs1, rs0) enable internal ram register banks as follows: rs1 rs0 internal ram register bank 0 0 bank 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 table 13. pcon special function register symbolic physical address address pcon smod arb req e gf1 gf0 pd idl 087h (msb) (lsb) symbol position function smod pcon7 double baud rate bit. when set to a 1, the baud rate is doubled when the serial port is being used in either mode 1, 2 or 3. arb pcon6 hld/hlda arbiter control bit * req pcon5 hld/hlda requestor control bit * e pcon4 (reserved) gf1 pcon3 general-purpose flag bit gf0 pcon2 general-purpose flag bit pd pcon1 power down bit. setting this bit activates power down operation. idl pcon0 idle mode bit. setting this bit activates idle mode operation. * see ``ext. memory dma'' description. note: if 1's are written to pd and idl at the same time, pd takes precedence. the reset value of pcon is (000x0000). 44
upi-452 absolute maximum ratings * ambient temperature under bias 0 cto70 c 2 storage temperature b 65 cto a 150 c voltage on any pin to v ss b 0.5v to v cc a 0.5v voltage on v cc to v ss b 0.5v to a 6.5v power dissipation1.0w ** notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. d.c. characteristics t a e 0 cto70 c; v cc e 5v g 10%; v ss e 0v symbol parameter min max units test conditions v il input low voltage b 0.5 0.8 v v ih input high voltage 2.0 v cc a 0.5 v (except xtal1, rst) v ih1 input high voltage 3.9 v cc a 0.5 v (xtal1, rst) v ol output low voltage 0.45 v i ol e 1.6 ma (note 1) (ports 1, 2, 3, 4) v ol1 output low voltage 0.45 v i ol e 3.2 ma (note 1) (except ports 1, 2, 3, 4) v oh output high voltage 2.4 v i oh eb 60 m a, v cc e 5v g 10% (ports 1, 2, 3, 4) 0.9 v cc vi oh eb 10 m a v oh1 output high voltage 2.4 v i oh eb 400 m a, v cc e 5v g 10% (except ports 1, 2, 3, 4 and 0.9 v cc vi oh eb 40 m a (note 2) host interface (slave) port) v oh2 output high voltage 2.4 v i oh eb 400 m a, v cc e 5v g 10% (host interface (slave) port) v cc b 0.4 v i oh eb 10 m a i il logical 0 input current b 50 m av in e 0.45v (ports 1, 2, 3, 4) i tl logical 1 to 0 transition b 650 m av in e 2v current (ports 1, 2, 3, 4) 45
upi-452 d.c. characteristics t a e 0 cto70 c; v cc e 5v g 10%; v ss e 0v (continued) symbol parameter min max units test conditions i li input leakage current g 10 m a 0.45v k v in k v cc (except ports 1, 2, 3, 4) i oz output leakage current g 10 m a 0.45v k v out k v cc (except ports 1, 2, 3, 4) i cc operating current 50 ma v cc e 5.5v, 14 mhz (note 4) i cci idle mode current 25 ma v cc e 5.5v, 14 mhz (note 5) i pd power down current 100 m av cc e 2v (note 3) rrst reset pulldown resistor 50 150 k x cio pin capacitance 20 pf 1 mhz, t a e 25 c (sampled, not tested on all parts) notes: 1. capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ols of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1- to-0 transitions during bus operations. in the worst cases (capacitive loading l 100 pf), the noise pulse on the ale line may exceed 0.8v. in such cases it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 2. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall before the 0.9 v cc specification when the address bits are stabilizing. 3. power down i cc is measured with all output pins disconnected; ea e port 0 e v cc ; xtal2 n.c.; rst e v ss ;db e v cc ;wr e rd e dack e cs e a0 e a1 e a2 e v cc . power down mode is not supported on the 87c452p. 4. i cc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl e 5 ns, v il e v ss a 0.5v, v ih e v cc b 0.5v; xtal2 n.c.; ea e rst e port 0 e v cc ;wr e rd e dack e cs e a0 e a1 e a2 e v cc .i cc would be slightly higher if a crystal oscillator is used. 5. idle i cc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl e 5 ns, v il e v ss a 0.5v, v ih e v cc b 0.5v; xtal2 n.c.; port 0 e v cc ;ea e rst e v ss ;wr e rd e dack e cs e a0 e a1 e a2 e v cc . explanation of the ac symbols each timing symbol has 5 characters. the first char- acter is always a `t' (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for: a: address. c: clock. d: input data. h: logic level high. i: instruction (program memory contents). l: logic level low, or ale. p: psen. q: output data. r: read signal. t: time. v: valid. w: write signal. x: no longer a valid logic level. z: float. example tavll e time for address valid to ale low. tllpl e time for ale low to psen low. 46
upi-452 a.c. characteristics t a e 0 cto70 c, v cc e 5v g 10%, v ss e 0v, load capacitance for port 0, ale, and psen e 100 pf, load capacitance for all other outputs e 80 pf external program and data memory characteristics symbol parameter 14 mhz osc variable oscillator units min max min max 1/tclcl oscillator frequency 3.5 14 mhz tlhll ale pulse width 103 2tclcl b 40 ns tavll address valid to ale low 25 tclcl b 55 ns (note 1) tllax address hold after ale low 36 tclcl b 35 ns tlliv ale low to valid instr in 185 4tclcl b 100 ns tllpl ale low to psen low 31 tclcl b 40 ns tplph psen pulse width 169 3tclcl b 45 ns tpliv psen low to valid instr in 110 3tclcl b 105 ns tpxix input instr hold after psen 00 ns tpxiz input instr float after psen 57 tclcl b 25 ns (note 1) taviv address to valid instr in 252 5tclcl b 105 ns tplaz psen low to address float 10 10 ns trlrh rd pulse width 329 6tclcl b 100 ns twlwh wr pulse width 329 6tclcl b 100 ns trldv rd low to valid data in 192 5tclcl b 165 ns trhdx data hold after rd 00 ns trhdz data float after rd 73 2tclcl b 70 ns tlldv ale low to valid data in 422 8tclcl b 150 ns tavdv address to valid data in 478 9tclcl b 165 ns tllwl ale low to rd or wr low 164 264 3tclcl b 50 3tclcl a 50 ns tavwl address valid to rd or wr low 156 4tclcl b 130 ns tqvwx data valid to wr transition 11 tclcl b 60 ns twhqx data hold after wr 21 tclcl b 50 ns trlaz rd low to address float 0 0 ns twhlh rd or wr high to ale high 31 111 tclcl b 40 tclcl a 40 ns tqvwh data valid to wr (setup time) 350 7tclcl b 150 ns note: 1. use the value of 14 mhz specification or variable oscillator specification, whichever is greater. 47
upi-452 external data memory read cycle 231428 19 external program memory read cycle 231428 20 48
upi-452 external data memory write cycle 231428 21 shift register mode timing waveforms 231428 22 49
upi-452 external clock drive symbol parameter min max units 1/tclcl oscillator frequency 3.5 14 mhz tchcx high time 20 ns tclcx low time 20 ns tclch rise time 20 ns tchcl fall time 20 ns note: external clock timings are sampled, not tested on all parts. serial port timingeshift register mode test conditions: t a e 0 cto70 c; v cc e 5v g 10%; v ss e 0v; load capacitance e 80 pf symbol parameter 14 mhz osc variable oscillator units min max min max txlxl (1) serial port clock cycle time 857 12tclcl ns tqvxh output data setup to clock rising edge 581 10tclcl b 133 ns txhqx output data hold after clock rising edge 26 2tclcl b 117 ns txhdx input data hold after clock rising edge 0 0 ns txhdv clock rising edge to input data valid 581 10tclcl b 133 ns note: 1. the tolerance of this signal is a function of the input oscillator frequency (txlxl e 12tclcl) external clock drive waveform 231428 23 ac testing input, output waveforms 231428 24 ac inputs during testing are driven at v cc b 0.5v for a logic ``1'' and 0.45v for a logic ``0''. timing measurements are made at v ih min. for a logic ``1'' and v il max. for a logic ``0''. float waveforms 231428 25 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh t g 20 ma. 50
upi-452 hld/hlda waveforms arbiter mode 231428 26 requestor mode 231428 31 hld/hlda timings test conditions: t a e 0 cto a 70 c; v cc e 5v g 10%, v ss e 0v; load capacitance e 80 pf symbol parameter 14 mhz osc variable oscillator units min max min max thmin hld pulse width 386 4tclcl a 100 ns thlal hld to hlda delay if 186 672 4tclcl b 100 8tclcl a 100 ns hlda is granted thhah hld to hlda delay 186 672 4tclcl b 100 8tclcl a 100 ns tamin hlda pulse width 386 4tclcl a 100 ns tahhl hlda inactive to 186 4tclcl b 100 ns hld active 51
upi-452 host port waveforms 231428 27 host port timings test conditions: t a e 0 cto70 c; v cc e 5v g 10%; v ss e 0v; load capacitance e 80 pf symbol parameter 14 mhz osc variable oscillator units min max min max tcc cycle time 429 6tclcl ns tpw command pulse width 100 100 ns trv recovery time 60 60 ns tas address setup time 5 5 ns tah address hold time 30 30 ns tds write data setup time 30 30 ns tdhw write data hold time 5 5 ns tdhr read data hold time 7 40 7 40 ns tdv read active to read 92 92 ns data valid delay tdr write inactive to read 343 4.8tclcl ns data valid delay (applies only to host control sfr) trq read or write active 150 150 ns to drqin or drqout inactive delay 52
upi-452 revision history document: upi-452 data sheet old revision number: 231428-005 new revision number: 231428-006 1. maximum clock rate was changed from 16 mhz to 14 mhz. this change is reflected in all maximum timing specifications. 2. the proper range of values for ithr has been changed from [ 0 to (cbp-2) ] to [ 0 to (cbp-3) ] to ensure proper setting of the input fifo request for service bit. see the following sections: input fifo channel, and input and output fifo threshold sfr (ithr & othr). 3. the proper range of values for othr has been changed from [ 1to (80h-cbp)-1 ] to [ 2to (80-cbp)-1 ] to ensure proper setting of the output fifo request for service bit. see the following sections: output fifo channel, fifo-external host interface fifo dma freeze mode, and input and out- put fifo threshold sfr (ithr & othr). 4. the following d.c. characteristics were deleted from the data sheet: v oh e 0.75 * v cc @ i oh eb 25 m a, v oh1 e 0.75 * v cc @ i oh e 150 m a, v oh2 e 3.0v @ i oh e 1 ma, and i cc1 e 15 ma @ v cc e 5.5v (87c452p). see d.c. characteristics table. 5. the parameter descriptions for thhah and thlal has been reversed and their maximum specification for clock rates less than 14 mhz has been changed from [ 4tclc a 100 ns ] to [ 8tclc a 100 ns ] . see hld/hlda timings. 6. tamin specification has been removed from the arbiter mode waveform diagram and added to the request- or mode waveform diagram. see hld/hlda waveforms. 7. minimum tdhr timing changed from 5 ns to 7 ns. 53

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